The present invention generally relates to digital signal processors. More particularly, the invention relates to external buses for digital signal processors. Still more particularly, the invention relates to arbitration for control of an external bus between multiple processor cores and direct memory access (DMA) controllers.
Microprocessors generally include a variety of logic circuits fabricated on a single semiconductor chip. Such logic circuits typically include a processor core, memory, and numerous other support components. Some microprocessors, such as digital signal processors (DSPs) provided by Texas Instruments, may include multiple processor subsystems each having its own processor core. Each processor subsystem includes memory and other support components for the associated processor core.
DSPs are generally sought for computationally intensive tasks because they have hardware specially designed for high performance computing. The processor subsystems which may be found on multi-core DSPs often have dedicated buses. For example, a processor subsystem may have a dedicated instruction bus that the processor core uses to retrieve program instructions from memory, a dedicated data bus that the processor core uses to retrieve data from memory, and a dedicated external input/output bus distinct from the instruction and data that the processor core uses for external communications.
The processor subsystems further include a dedicated direct memory access (DMA) memory bus distinct from the aforementioned buses that a DMA controller uses to move data in and out of the memory without any intervention from the processor core. The DMA controller also controls a dedicated external I/O bus. The external I/O buses of the processor core and the DMA controller are coupled to an external port that is shared with the other processor subsystems. The external port is a limited resource that the DMA controllers and the processor cores must share, hence it would be desirable to have an efficient arbitration method for determining which component should obtain control of the external port.